6-Layer PCB Design - Analog Satellite Control System

6-Layer PCB Design for Analog Satellite Control System

Project Repository: https://github.com/SimonAulet/portfolio/tree/main/PCB

Contains all project files: KiCad schematics, PCB designs, LTSpice simulations, datasheets, and component libraries for direct import.

Context

Group development of an analog satellite control system implemented with discrete components. The system integrates orientation detection through photoresistors, thermal sensing, analog PWM generation, servomotor positioning, timing circuits, analog latches, and autonomous control logic.

My Contribution

Comprehensive KiCad Design: Integration and physical development of the system from laboratory-implemented modules. This involves creating the unified schematic in KiCad, strategic selection of components compatible with industrial assembly, footprint and 3D model management, implementation of design classes for signal separation (analog, digital, power), critical routing, and exhaustive validation through ERC/DRC, culminating in a 6-layer PCB ready for manufacturing.

Analog Simulation and Validation: LTSpice simulation of key stages: hysteresis comparators (Schmitt trigger), analog PWM generator, timing circuits, decision logic for power source switching via relays, and latches implemented with NPN transistors.

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Phase 1: Architecture

General System

The design was structured into 6 modular subsheets, each encapsulating a specific function:

• Active filtering for LDR sensor signal conditioning
• Orientation sensing for eclipse/position detection
• Thermal control with LM35 sensing and actuation
• Solar panel deployment with PWM control and verification
• Deployment verification using 555 timers
• Power source selector for automatic switching between solar/battery

Communication between modules was established through coherently named signals using prefixes. For example A_ → Sensitive analog signals, C_ → Commands and control signals, F_ → Feedback, L_ → LED indicators, etc. and suffixes to indicate input (_I) or output (_O)

Detailed Schematics

Component Selection

Each component was chosen considering electrical specifications, availability, layout implications, and thermal/mechanical requirements. We attempted to use all from the same manufacturer (Texas Instruments) when possible:

Component	Manufacturer	Key Features	Selection Reason
LM35	Texas Instruments	Sensor de temperatura, TO-220	Allows direct screwing to batteries/heat sources for precise measurement
LM358B	Texas Instruments	Op-amp dual, SMD, 0.1µF en Vcc	Proven stability, integrated compensation, compact package
CSD17577Q5A	Texas Instruments	MOSFET N-ch, 25V, 6.7mΩ	Switching efficiency, low Rds(on), optimal for relays
RT314009	TE Connectivity	Relay 9V/16A, 1 Forma C	Current capacity for battery switching, coil compatible with 9V

Layout considerations: SMD packages were prioritized to reduce parasitic inductances, while components like the LM35 in TO-220 located in external sensors allowed robust mechanical mounting where direct thermal transfer was required.

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Phase 2: Physical Implementation - 6-Layer PCB

Stackup Strategy

The 6-layer distribution was optimized to ensure signal integrity and facilitate debugging, with clear function separation:

Layer	Designation	Main Content	Key Consideration
1	F.Cu (Top)	Critical analog signals	Accessible for measurement, short traces
2	In1.Cu	Continuous ground plane	Low impedance reference
3	In2.Cu	Power distribution	Separation between clean and general power
4	In3.Cu	Control signals and setpoints	Isolation from analog paths
5	In4.Cu	Interconnections and LEDs	Utility layer
6	B.Cu (Bottom)	Long-distance analog routes	"Highways" with predictable routing

Layer Visualization

Routing Methodology

Routing followed a strict hierarchy, prioritizing integrity over convenience:

1. Ground - Reference establishment with multiple vias
2. Power - Traces dimensioned according to required current. Separation of IC power (power_clean) from general power
3. Feedback signals - Direct and protected routes
4. Analog signals - Length minimization and crossing avoidance
5. Control and LEDs - Completion of interconnections

This sequence ensured that the most sensitive signals had optimal routes before compromising space with secondary functionalities.

External Subsystems and Connectivity

Key Design Points

• Effective domain separation: The 63 signals organized into classes allowed applying consistent and automated design rules.
• Successful hierarchical routing: Starting with reference and power, then critical signals, finally secondary functionalities.
• Built-in debugging: All critical signals accessible on external layers, with space for test points where necessary.
• Exceeded specification compliance: The final design exceeds the minimum clearance and trace width requirements of the selected manufacturer.

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Simulation and Analytical Validation

Each critical subsystem of the design was modeled and validated in LTSpice before any physical implementation. Starting from functional requirements —hysteresis comparators, analog latches, timers, and PWM generators— models were built using real components, such as the LM358 opamp configured according to its Texas Instruments datasheet, and PWL signals to simulate operational conditions.

This simulation process allowed optimizing component values, verifying design margins, and predicting system behavior with high accuracy. The results were then successfully correlated with breadboard measurements using a high-end Tektronix oscilloscope, establishing a solid foundation for the final PCB design.

1. Hysteresis Comparator (Schmitt Trigger)

Hysteresis was implemented to eliminate switching oscillations with noisy or slowly varying signals. The circuit was modeled in LTSpice and characterized both analytically and experimentally.

The simulation with a triangular ramp confirms that switching occurs with a 425 mV difference between rising and falling edges, in excellent agreement with the theoretical calculation of 430 mV. This ensures noise immunity and stability in threshold detection.

The waveforms demonstrate the design's effectiveness: while the comparator without hysteresis shows multiple unwanted switching events when crossing the threshold, both Schmitt trigger configurations maintain a clean and stable output even with noisy input signals.

2. Analog Timing and Alarm Logic

The timing subsystem integrates a 555 timer, a custom anti-latch circuit, and alarm enable logic to ensure error signals activate only under valid conditions.

Latch-to-Pulse Converter

Original design that solves a specific requirement: the 555 needs an edge, not a sustained signal. Implemented with an LM358 and 5 µF capacitor, it generates a short pulse on each rising edge of the input, ignoring its subsequent state. Used twice in the system (for opening and closing panel verification).

555 Timer Behavior

The 555 operates with active-low output. The simulation shows two activation modes: through reset signal (undesired, requiring filtering) and through a valid trigger after the timing period.

Alarm Enable Logic

Implemented with an opamp as comparator, it acts as an analog AND gate to avoid false positives during system reset. Only when the trigger is active (low) and the reset is inactive (high) is the alarm signal generated.

3. Analog Latch with NPN Transistors

Simple latch implemented with two cross-coupled NPN transistors that maintains a stable state (ON/OFF) until receiving an opposite switching signal. Used to retain the deployment state of solar panels.

The latch responds correctly to input pulses, maintaining the last activated state without additional consumption until the next switching. The simulation confirms stable transition between states without oscillations.

4. Power Source Switching with MOSFET

Control stage for relay activation through MOSFETs, managing selection between solar source and batteries. The simulation focuses on MOSFET behavior, as the relay operates as a controlled inductive load.

The simulation confirms that the circuit correctly detects when illumination (simulated as variable resistance) crosses the established threshold, generating a clean transition in the comparator output.